CMOS

Static CMOS InverterStatic CMOS Inverter

CMOS (pronounced "see-moss"), which stands for complementary metal-oxide-semiconductor, is a major class of integrated circuits. CMOS chips include microprocessor, microcontroller, static RAM, and other digital logic circuits. The central characteristic of the technology is that it only uses significant power when its transistors are switching between on and off states. Consequently, CMOS devices use little power and do not produce as much heat as other forms of logic. CMOS also allows a high density of logic functions on a chip.

The word "complementary" refers to the fact that the design uses pairs of transistors for logic functions, only one of which is switched on at any time.

The phrase "metal-oxide-semiconductor" is a reference to the nature of the fabrication process originally used to build CMOS chips. That process created field effect transistors having a metal gate electrode placed on top of an oxide insulator, which in turn is on top of a semiconductor material. Instead of metal, today the gate electrodes are almost always made from a different material, polysilicon, but the name CMOS nevertheless continues to be used for the modern descendants of the original process. (See also MOSFET.)

Development history

CMOS circuits were invented in 1963 by Frank Wanlass at Fairchild Semiconductor. The first CMOS integrated circuits were made by RCA in 1968. Originally a low-power but slow alternative to TTL, CMOS found early adopters in the watch industry and in other fields where battery life was more important than speed. Some twenty-five years later, CMOS has become the predominant technology in digital integrated circuits. This is essentially because area occupation, operating speed, energy efficiency and manufacturing costs have benefited and continue to benefit from the geometric downsizing that comes with every new generation of semiconductor manufacturing processes. In addition, the simplicity and comparatively low power dissipation of CMOS circuits have allowed for integration densities not possible on the basis of bipolar junction transistors.

Early CMOS circuits were very susceptible to damage from electrostatic discharge (ESD). Subsequent generations were thus equipped with sophisticated protection circuitry that helps absorb electric charges with no damage to the fragile gate oxides and PN-junctions. Still, antistatic handling precautions for semiconductor devices continue to be followed to prevent excessive energies from building up. Manufacturers recommend using antistatic precautions when adding a memory module to a computer, for instance.

On the other hand, early generations such as the 4000 series that used aluminum as a gate material were extremely tolerant of supply voltage variations and operated anywhere from 3 to 18 volts DC. For many years, CMOS logic was designed to operate from the then industry-standard of 5 V imposed by TTL. By 1990, lower power dissipation was usually more important than easy interfacing to TTL, and CMOS voltage supplies began to drop along with the geometric dimensions of the transistors. Lower voltage supplies not only saved power, but allowed thinner, higher performance gate insulators to be used. Some modern CMOS circuits operate from voltages below one volt.

In the early fabrication processes, the gate electrode was made of aluminum. Later CMOS processes switched to polycrystalline silicon ("polysilicon"), which can better tolerate the high temperatures used to anneal the silicon after ion implantation. As of 2004 there is some research into using metal gates once again, but all commonly used processes have polysilicon gates.

Technical details

CMOS (complementary metal oxide semiconductor) refers to both a particular style of digital circuitry design, and the family of processes used to implement that circuitry on integrated circuits (chips). CMOS logic on a CMOS process dissipates less energy and is more dense than other implementations of the same functionality. As this advantage has grown and become more important, CMOS processes and variants have come to dominate, so that as of 2004 the vast majority of integrated circuit manufacturing by dollar volume is on CMOS processes.

Structure

CMOS logic uses a combination of p-type and n-type metal-oxide-semiconductor field effect transistors (MOSFETs) to implement logic gates and other digital circuits found in computers, telecommunications and signal processing equipment. Although CMOS logic can be implemented with discrete devices (for instance, in an introductory circuits class), typical commercial CMOS products are integrated circuits composed of millions (or hundreds of millions) of transistors of both types on a rectangular piece of silicon of between 0.1 and 4 square centimeters. These bits of silicon are commonly called chips, although within the industry they are also referred to as die, perhaps because they are the result of dicing (that is, cutting up) the circular silicon wafer which is the basic unit of semiconductor device fabrication.

In CMOS logic gates, as in NMOS logic gates, a collection of n-type MOSFETs is arranged in a pull-down network between the output and the lower-voltage power supply rail (often named Vss). Instead of the load resistor of NMOS gates, CMOS gates have a collection of p-type MOSFETs in a pull-up network between the output and the higher-voltage rail (often named Vdd). The p-type transistor network is complementary to the n-type transistor network, so that when the n-type is off, the p-type is on, and vice-versa.

CMOS logic dissipates less power than NMOS logic because CMOS dissipates power only when switching (dynamic power). On a typical ASIC in a modern 90 nanometer process, switching the output might take 120 picoseconds, and happen once every ten nanoseconds. NMOS logic dissipates power whenever the output is low (static power), because there is a current path from Vdd to Vss through the load resistor and the n-type network.

P-type MOSFETs are complementary to n-type because they turn on when their gate voltage goes sufficiently below their source voltage, and because they can pull the drain all the way to Vdd. Thus, if both a p-type and n-type transistor have their gates connected to the same input, the p-type MOSFET will be on when the n-type MOSFET is off, and vice-versa.

As an example, shown on the right is a circuit diagram of a NAND gate in CMOS logic. If both of the A and B inputs are high, then both the n-type transistors will conduct, neither of the p-type transistors will conduct, and a conductive path will be established between the output and Vss, bringing the output low. If either of the A or B inputs is low, one of the n-type transistors will not conduct, one of the p-type transistors will, and a conductive path will be established between the output and Vdd, bringing the output high.

Another advantage of CMOS over NMOS is that both low-to-high and high-to-low output transitions are fast since the pull-up transistors have low resistance when switched on, unlike the load resistors in NMOS logic. In addition, the output signal swings the full voltage between the low and high rails. This strong, more nearly symmetric response also makes CMOS more resistant to noise.

See Logical effort for a method of calculating delay in a CMOS circuit.

Power

CMOS circuits dissipate power by charging and discharging the various load capacitances (mostly gate and wire capacitance, but also drain and some source capacitances) whenever they are switched. The charge moved is the capacitance multiplied by the voltage change. Multiply by the switching frequency to get the current used, and multiply by voltage again to get the characteristic switching power dissipated by a CMOS device: P = CV2f.

A different form of power consumption became noticeable in the 1990s as wires on chip became narrower and the long wires became more resistive. CMOS gates at the end of those resistive wires see slow input transistions. During the middle of these transitions, both the NMOS and PMOS networks are partially conductive, and current flows directly from Vdd to Vss. The power thus used is called crowbar power. Careful design which avoids weakly driven long skinny wires has ameliorated this effect, and crowbar power is nearly always substantially smaller than switching power.

Both NMOS and PMOS transistors have a threshold gate-to-source voltage, below which the current through the device drops exponentially. Historically, CMOS designs operated at supply voltages much larger than their threshold voltages (Vdd might have been 5 V, and Vth for both NMOS and PMOS might have been 700 mV). As supply voltages have come down to conserve power, voltage thresholds have had to come down as well. The exponential current curve has not changed, however, and as a result a modern NMOS transistor with a Vth of 200 mV has a significant subthreshold leakage current. Designs (e.g. desktop processors) which try to optimize their fabrication processes for minimum power dissipation during operation have been lowering Vth so that leakage power begins to approximate switching power. As a result, these devices dissipate considerable power even when not switching.

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NMOS

nMOS logic uses n-type metal-oxide-semiconductor field effect transistors (MOSFETs) to implement logic gates and other digital circuits. nMOS transistors have three modes of operation: cut-off, triode, and saturation (sometimes called active).

The n-type MOSFETs are arranged in a so-called "pull-down network" (PDN) between the output and low-voltage (ground) rail, while a resistor is placed between the output and the high-voltage rail. The circuit is designed such that if the desired output is low , then the PDN will be active, creating a current path between the low-voltage rail and the output.

As an example, here is a NOR gate in nMOS logic. If either input A or input B is high (logic 1, = True), the respective MOS transistor acts as a very low resistance between the output and the low-voltage supply rail, forcing the output to be low (logic 0, = False). When both A and B are high, both transistors are conductive, creating an even lower resistance path to ground. The only case where the output is high is when both transistors are off, which only occurs when both A and B are low, thus satisfying the truth table of a NOR gate:

While nMOS logic is easy to design and manufacture (a MOSFET can be made to operate as a resistor, so the whole circuit can literally be made with one type of component), it has several shortcomings as well. The worst problem is that a DC current flows through an nMOS gate when the PDN is active, that is whenever the output is low. This leads to static power dissipation even when the circuit sits idle.

A B A NOR B
0 0 1
0 1 0
1 0 0
1 1 0

Also, nMOS circuits are slow to transition from low to high. When transitioning from high to low, the transistors provide low resistance, and the capacitative charge at the output drains away very quickly. But the resistance between the output and the high supply rail is much greater, so the low to high transition takes longer. Using a resistor of lower value to speed up the process is a mixed blessing as this also increases power dissipation. Additionally, the asymmetric behavior makes nMOS circuits susceptible to noise